1. Field of the Invention
The invention relates to electronic integrated circuit chips. Specifically, the invention relates to a method for forming conductive vias in semiconductor wafers and die to form high density electrical interconnection structures and a device made from the method.
2. Description of the Prior Art
Industry continues to seek devices that allow high-density electronic circuitry to occupy a very small space. Satellites, aerospace applications, military weaponry and surveillance, and consumer electronics all require ever-smaller electronic circuitry. It has been determined that stacking layers of electronic circuitry and vertically interconnecting the layers provides a significant increase in circuit density per unit area. Examples of related three-dimensional stacking inventions are disclosed in a number of patents issued to common assignee, Irvine Sensors Corp., such as U.S. Pat. No. 6,560,109, U.S. Pat. No. 4,525,921, and U.S. Pat. No. 4,646,128, each of which is incorporated herein by reference.
High-speed electronic applications operating in the gigahertz range also create unique circuit design concerns with respect to capacitance, inductance and “time of flight” for electron travel. Shorter lead lengths within a high-speed circuit help minimize these design concerns.
It has been determined that stacking of individual, unpackaged, integrated circuit die allows for a very small form factor, while achieving ultra-high circuit density and minimal lead lengths. But stacking of individual circuit die undesirably includes yield problems when a stack includes a failed layer, as well as complications related to interfacing, wire bonding and/or side-bussing of stacked integrated circuit die. Additionally, wirebonding interface interconnects creates longer lead lengths with associated problems of cross talk and electron time of flight.
Conductive via interconnects can be used beneficially to electrically connect a semiconductor layer with electronic circuitry with an adjacent layer but, because of the fabrication processes associated with via formation, existing electronic circuitry can be damaged during via formation. This is because via formation presently occurs after the electronic circuitry is formed on the semiconductor wafer of substrate. Because of the photolithographic and etching processes associated with via formation, the fragile electronic circuitry on a die or wafer can easily be damaged.
Therefore, a need exists in the art which allows for the efficient, scalable stacking of integrated circuit die which reduces yield problems, manufacturing concerns and problems associated with wire bonding and unnecessary lead lengths.